
module BReg(iClk, iReset, iBReg, oBReg);
	input [31:0] iBReg;
	input iReset, iClk;
	output [31:0] oBReg;
	reg [31:0] oBReg;

	always @ (posedge iReset or posedge iClk)
	begin
		if(iReset)
			oBReg <= 32'b0;
		else
			oBReg <= iBReg;
	end
	
endmodule